Senior Verification Engineer
  
8+ years relevant Design Verification experience
Expertise in digital design and verification tools; RTL design using Verilog & verification with System Verilog and UVM
Specification, Design and Verification of High Speed PHY IP based on communication protocols (PCIe, Ethernet)
Verification from initial concept/specification through final verification of conformance to customer specifications using Coverage metric Implementation, Tracking and Closure
Work with cross-functional global teams
Experience of Assertion Based Formal Verification benefitial
Excellent problem-solving skills and ability to work cooperatively in a team environment