E-71139
Area of expertise: Analog Layout
Core Technologies: Consumer Electronics
Experience: 22 years
Time On Site: 0%
Considerable experience in Analog Layout Custom Analog IC layout design and verification Cadence Virtuoso up to IC6.1.7, Assura, Calibre Module and chip level IC layout, process nodes: 28nm to 2um Experience working on band-gap references, Oscillators, EEPROM, OP-AMP, ADC, SRAM, ROM, RF detector, Comparators, LDOs, pseudo resistors working on the top level. Digital Layouts: Standard cells, Pad cells, place and route of multiple digital blocks including one for single and multiple channels touch sensors.
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Unit 8B, Galway Technology Centre, Galway, Ireland