Technical Skills:
- FPGA/ASIC Design Verification
- UVM
- SystemVerilog
-  Formal Verification Training in JasperGold
-  SystemVerilog Assertions Training
-  Python
-  Embedded Systems

- Verification Methodologies: Randomized Constraint Testing, Direct Testing, Black Box Testing, Formal 
 Verification(basics), Universal Verification Methodology, Open Verification 
 Methodology
- Verification Languages: SystemVerilog, SystemVerilog assertions(basics), Tcl
-  Design Languages: Verilog - basics, VHDL - basics
-  Revision and Control Systems: SVN, Git (Gitlab, Github)
-  Tools: Xcelium, Jasper, vManager, VCS, Verdi, Questa, Jira, Python
-  Protocols: AXI (Lite, Stream), CXL (.mem & .io), Avalon, PCIe gen 5 (mostly address 
 translation), DTI
- Operating Systems: Linux