E-49593
Area of expertise: ASIC Design
Core Technologies: 5G
Experience: 20 years
Time On Site: 50%
Front-end digital design and verification engineer with experience in developing IP/ASIC/FPGA using Verilog(/SystemVerilog) and VHDL. The core competencies are RTL (IP) design and verification including structural tests (linting, formal verification, CDC, test coverage etc) as well as gate level simulations. Affinity with SoC and analog modules integration aspects, interfacing to DfT and back-end teams, configuration management expertise
Contact Us
+353 91 444 168
info@chipright.com
Unit 8B, Galway Technology Centre, Galway, Ireland