Senior Product Validation Manager

 	
Experience in Physical Verification (Digital Sign-Off) and Product Validation (Analog Custom IC) domains.
 	
Proven Technical Lead & Project Manager with a track record of leading complex technical projects in the semiconductor
industry.
 	
Extensive hands-on experience in Full Chip Verification flows DRC/LVS/ERC/Density/Fill using Pegasus/PVS solutions with Innovus & Virtuoso platforms, enabling Cadence Physical Verification flows on advanced node technologies (2nm/3nm/5nm/7nm).
 	
Specialized in Custom-IC Layout Design, with expertise in Custom level routing & standard cell placement techniques across various technologies, and proficient in physical verification (DRC/LVS) and validation of respective tools.
 	
Experienced in analog front-end design environments (Virtuoso ADE) and simulators.
 	
Expertise in people management: Managed a team of engineers across geographies.