ASIC Design and Verification Engineer

 	
 -Strong coverage-driven, UVM SystemVerilog module-level verification experience
 	
 -Basic Specman experience
 	
 -Strong Verilog IP design expertise
 	
 -Dedicated, hard-working team player with a high awareness of project needs and service orientation
 	
 -Professional skills: IP and SoC verification, ASIC Design
 	
 -Programming languages: SystemVerilog/UVM, Specman, Verilog, VHDL
 	
 -Tools: Cadence IUS, Simvision, Vmanager, Synopsys VCS, Simvision, DVE