-Experienced SoC Design Verification Engineer with a strong background in verifying complex Verilog and VHDL IP for SOCs, ASICs and FPGAs
 	
 -Proficient in VHDL, Verilog, SystemVerilog and UVM
 	
 -Proficient using Siemens EDA (Mentor Graphics), Synopsys, Cadence simulators and OneSpin 360
 	
 -Proficient using DVT Eclipse IDE, DVT Debugger, ICManage and Svn
 	
 -Proficient in AMBA AXI and ACE bus protocols
 	
 -Experience in C++, IPXact, Perl, and Tcl
 	
 -Experience using Intel Quartus Prime, LeonardoSpectrum, Xilinx ISE, Synplify Pro, Tanner S-EDIT and L-EDIT