Digital Verification Engineer

 	
 -Expertise in module and top-level verification projects using different languages/methodologies, including SystemVerilog (UVM) and C, C++ and PSS
 	
 -Development of the verification environment from scratch on several projects
 	
 -Experienced in leading a team of up to 10 members
 	
Technical Skills:
 	
 -Programming languages: C, C++, Pascal, System Verilog, Verilog, Python
 	
 -Type of verification: Digital, Mixed-signal, Power aware (UPF)
 	
 -Scripting: Python, Perl, TCL, Makefile, Linux shell
 	
 -HDL simulators: NCSim (Cadence), VCS (Synops)
 	
 -Simulation and Management Tools: vManager, vPlan, IMC, Verdi, Simvision
 	
 -Verification methodologies and concepts: UVM, Directed testing, code coverage, functional coverage, assertions, error injections
 	
 -Application software: LibreOffice, Microsoft Office
 	
 -Other: Perforce, Subversion, Cliosoft SOS, Design Sync, Orcad Pspice, MATLAB
 	
 -Protocol expertise: USB 3.2, PCIe 4.0, AHB, APB, AXI, SPI