Senior Design Verification Engineer

 	
 -Experience with verification requirements, test plans, and test procedures
 	
 -Experience in creating UVM testbench architectures
 	
 -Worked on verifying communication protocols
 	
 -Worked on verifying custom design codes
 	
 -Experience with Formal Verification (JasperGold Superlint, FPV, UNR etc.)
 	
 -Experience with assertions and functional coverage
 	
 -Experience with preparing verification plans
 	
 -Implement randomized sequences, tests, test benches, and their components
 	
Technical Skills:
 	
 -UVM, SystemVerilog
 	
 -SystemVerilog Assertions (SVA)
 	
 -JasperGold Formal Verification Apps (Superlint, FPV, UNR, COV etc.)
 	
 -Cadence SimVision
 	
 -QuestaSim
 	
 -Object-orientated programming (OOP)
 	
 -C, C++, Scripting
 	
 -vManager
 	
 -JIRA
 	
 -DOORS