-Experience with Block and Top level verification
 	
-Experience with SystemVerilog/UVM and VerilogAMS
 	
-Knowledge of APB, AHB, SPI, SVCI, SmaRT, customer-specific serial and parallel audio protocols
 	
-Experience with Cadence tools like Simvision, Virtuoso, Vmanager
 	
-Experience with DesignSync, Git, Perforce, SVN
 	
-Familiar with Perl/Tcl/Python/Ruby scripting languages
 	
-Has been working for demanding clients, in a multinational environment, with strict deadlines