Digital Design Team 01

Experience level: 50 years

Experience

This team consists of 4 Engineers - 1 team lead and 3 experienced RTL Design Engineers (VHDL & VERILOG). They have a combined total of 50+ Years of experience in ASIC/FPGA design. The team have worked on 7 complex SoC Level ASIC designs (up to 4 million gates) all designs delivered right first time

Expertise

Core Expertise: ASIC & FPGA IP Design- Telecomms

Tools

Experience of core team includes System Architecture ARM, AMBA, I2C, SPI, MicroProcessor Interfaces Telecom Interfaces OTN, SONET, SDH, PDH, GFP, Datacomms interfaces ASIC FPGA DESIGN and implementation Texas Instruments, LSI, STM, XILINX, ALTERA LATTICE SoC level Design and Integration ARM. Power PC, NIOS Micro Blaze cores Embedded software design RTOS, Linux