-Mixed Signal Physical Design Engineer with a number of years experience.
 	
 -Proficient in Digital and Analog mixed signal Physical IC design, ICC, Olympus, Virtuoso, STA, CTS, DRC, RDL Routing, Floor-planning, Timing closure, concurrent clock-data optimization, ESD, EM, UPF and IR drop design, Tool flow creation with report and monitoring architectures, Project, technology, library and MCMM constraint setup, Verilog-AMS connect modules, boundary constructs, Analog instrumentation and PLL design
 	
 -TSMC 28nm / 16nm / 12nm Finfet / ST 28nm process RTL to GDS STA and CTS Multiple corner timing closures Calibre DRC, LVS and PERC Silicon ESD protection, Pad ring and RDL construction Hierarchal UPF power structures Unix, TCL and Makefile flow scripting FPGA Hardware / Verilog + VHDL