-Responsible for MBIST, BISR (including controller), and EDT-OCC-SSN insertion using Tessent and Xcelium for pattern simulations
 	
 -Implemented shared bus MBIST for ARM cores
 	
 -Implemented APB-based Mission Mode and embedded boundary scan on IO's and PHY IP's
 	
 -Worked on next generation of low-power IoT chips
 	
 -DFT insertion and verification for hierarchical design nodes and top level
 	
 -ATPG and supporting scan insertion for synthesis unit delay and sdf based atpg simulations and debug at block level and top level
 	
 -Setting up and supporting designers with block-level synthesis and running top-level synthesis on the latest tech node