E-69187

Area of expertise: Analog Mixed Signal Verification
Core Technologies: Automotive
Experience: 8 years
Time On Site: 0% 
    
 	
  • Mixed Signal Verification Engineer with experience in:
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  • -Writing UVM tests in SystemVerilog
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  • -Edit of the UVM base classes
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  • -Behavioral models in SystemVerilog and Verilog-AMS
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  • -Digital, Analog and Mixed-signal simulations in Cadence
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  • -Design support (design, modelling, verification) engineer for various automotive projects
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  • -Mixed-Signal Verification of PMIC products
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  • -Verification for different blocks (LDOs, Buck and Boost converters, Bandgap, voltage monitoring blocks
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  • -Experience in projects: Power switches, Linear regulators, Power converters.
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