-Years of practical hands-on experience with digital design and verification in VHDL, Verilog, SystemVerilog.
 	
 -UVM, OVM, PSS, SVA, formal
 	
 -Strong analytical and debugging skill.
 	
 -Verification IP development in SystemVerilog. Reference model development in
SystemVerilog and SystemC.
 	
 -Coverage metrics definition. Coverage analysis and improvement.
 	
 -Test bench performance analysis and improvement.
 	
 -EDA tools: Cadence Xcelium/Incisive, Vmanager, Vplanner, Jasper, Perspec,
Mentor's QuestaSim, Infact, Synopsys VCS, Vivado
 	
 -HDL: VHDL, Verilog, SystemVerilog
 	
 -Programming language: C/C++, SystemC, Matlab/simulink, Java, PSS-DSL
 	
 -Scripting language: Perl, bash, TCL
 	
 -Revision control tools: GIT, SVN, Clearcase, CVS, etc. and continuous integration (Jenkins)
 	
 -DSP algorithm block design and verification. Clock domain crossing design, pipelined design
for high-speed requirements. Low power design with and multi-VT cells
 	
 -Frontend digital ASIC synthesis flow.