-Digital Verification Engineer
 	
-Strong expertise in UVM, System Verilog, Verilog and Specman (e/eRM) languages
 	
-Architecting & developing Block/Sub-system/SoC testbenches from scratch using UVM SV
 	
-SoC, Sub-system, IP level functional and Netlist (GLS) verification of complex HDL designs
 	
-HW-SW Co-Verification of SoC's involving ARM processor/s integrated with complex HDL designs
 	
-FPGA Design and Verification using Xilinx tools viz. Vivado
 	
-Formal Verification using SVA and formal tools
 	
-Low Power Design verification with UPF
 	
-Python, Perl, Shell, TCL, Makefile scripting languages and flow development
 	
-Highly experienced in implementing new technologies and structurally building systems from ground-up
 	
-Protocol knowledge:
 	
 -Bus protocols: AMBA (APB, AHB, AXI3/4, ACE, AXI4-Stream), OCP
 	
 -Memory protocols: DDR2
 	
 -Serial protocols: PCIe Gen2/3/4, USB2/3, JTAG, SPI (OSPI, QSPI), UART, I2C
 	
 -Networking protocols: NoC (Network on Chip), Gigabit Ethernet, Interlaken (ILKN)