Full Custom Analog &Mixed Signal Layout Design.
High Speed Layout, DRC, LVS, DFM, PEX, IO pads, Standard Cell Design & layout, Transistor Folding, Matching techniques, shielding, parasitic minimization, Floor planning, signal integrity, Latch Up, antenna, ESD, IP Integration. 
Library Characterization, Backend view generation
Front End Views- Digital Models- Verilog and VHDL, Timing Views, Synopsys, Dot Libs, Backend Views ? Abstract, LEF, GDS, 
Extracted C and RC netlists - PEX views, Post Layout Changes  etc.
ESD, RF & Analog Layout: Good Knowledge of ESD protection like HBM & CDM models.
Layout of analog/RF blocks, perform verification and extraction of the layouts blocks and closely work with the designers to optimize layouts, Floor-planning of IP/Chip level complex designs down to layout of analog sub-blocks, area optimization. 
Tools: Cadence Virtuoso, Caliber, Assura, Synopsys layout Editor. totem for EM and IR 
fixes. Apache, Model Sim, layout  editor, Spector. ESD