Lead Design Verification & team leading experience
SOC/IP/Block level verification - UVM, OVM, RVM, SystemVerilog, Verilog.
SOC co-verification and automation using ADSP/Blackfin processor.
Firmware development experience for FPGA emulation using ADSP-218x based design
Complete Product / Project life cycle technical / team leading experience
Product development experience in Customer premises equipment for corDECT standards.
Onsite working experience in Finland(20 month), China(1 month) and UK(10 years)

HDL Languages: Verilog,VHDL, SystemVerilog
Simulation Tools: Synopsys-Vcs,Cadence,Questa
SW Languages: C,C++, Assembly (ADSP), Microcode (Network Processor), Java
Methodology: UVM,OVM,RVM
Protocols: Image Processing, Signal processing, Ethernet, ATM, IPv4, EOAM, DECT, USB
Processor Arch: ADSP2181(DSP), APP650(Network), MPC8560(Communication), Blackfin(DSP)
Tools: ClearCase, GIT, Perforce, SVN, Jenkins
Scripting: Perl, Python, Shell