-Custom analog and mixed-signal as well as RF IC layout design and verification experience, using proper layout design techniques  such as matching, isolation, shielding, etc, together with applying DFM rules and taking care of latch-up, WPE, EM, IR drop and other effects during the design.
-Cadence Virtuoso up to IC6.1.7 (L/XL/GXL), PVS, Assura (DRC, LVS), QRC, K2 (DRC), 
- Mentor Calibre (nmDRC, nmLVS, RVE), StarRC, DesignSync, Design Manager, SOS design manager
- TI 130nm (CMOS), 180nm (BiCMOS), 250nm (BiCMOS);
- Tower Jazz ? 180nm (BiCMOS- SiGe); 
- GF- 55nm (CMOS) 
- XFAB ? 180nm (CMOS)
- TSMC 130nm (CMOS), 55nm(CMOS), 7nm(FinFET)
- NXP 140nm (CMOS)