-An experienced ASIC Engineer with over 15 years in the industry, specializing in adapting complex digital signal processing algorithms to hardware platforms, proficient in block-level, and system-level design, with a profound understanding of on-chip communication
 	
-Known for strong organisational skills, self-discipline, and a successful track record in project management and remote work environments
 	
-Holds a strong academic background that supports a solid technical foundation in digital logic design
 	
-General System and Block Level Design, DSP, Floating Point and Fixed Point Arithmetic, Formal Verification, On-chip AMBA communication, Technical Writing, Project Management Tools Cadence Incisive, Xilinx Vivado, Cocotb, Numpy, Scikit-learn, Intel Quartus II, Cadence Jasper, Synopsys Spyglass, Cadence Palladium XP, ModelSim, Git, GNU Make, Matlab Languages Verilog, Python, Tcl, VHDL, C, C++, SystemVerilog Assertions