Experienced Digital Design Engineer with proven record in the semiconductor industry. I have 
demonstrated success in developing and managing IPs, RTL implementation and post silicon testing. Significant experience in digital design targeting ASIC/FPGA.
dsPIC33A peripheral IP and chip-level design
Memory controllers (NVM, ROM, RAM) and MBISTs
Crypto co-processors (DES, AES, SHA) and security specific digital design
nterface protocols (UART, SPI, I2C, I3C)
ARM AMBA protocols (AXI, AHB, APB)
ALTERA Quartus and ALTERA NIOSII SoC
Conformal LEC
ATPG and DFT
Questa Formal Apps
SystemVerilog and VHDL
Pre/post silicon tests in C and x86 assembly
Python prototyping of digital circuits
Integrating third party IPs
Synopsys Design Compiler
Synopsys Formality
Synopsys Spyglass and VC Spyglass Lint/CDC/RDC
Cadence Xcelium
Siemens QuestaSim, Visualizer
Post silicon production results analysis in Python.
FPGA IP prototyping
Microcontroller/