E-25621

Area of expertise: Analog Layout
Core Technologies: Automotive
Experience: 11 years
Time On Site: 0% 
Senior Analog IC Layout Engineer
-Custom Analog IC layout design and verification
-Cadence Virtuoso up to IC6.1.x, Assura, Calibre, PVS, Verilog A/AMS
-Module and chip level IC layout, tech. 22 ? 350 nm
-Multiple power management blocks, ADCs, DACs, PLLS, RF blocks

Share this profile