Extensive knowledge of front-end ASIC verification flow from design verification to silicon bring up
 Expertise in the development of UVM based Coverage driven constraint random verification Environment
 Expertise in the development of verification IP components Agent, Driver, Monitor, and Scoreboard using 
UVM Methodology
 Expertise in developing C solvers for scoreboard checking and using it through System Verilog DPI
 Expertise in the usage of VIP at SoC, Subsystem, and IPs verification environment, simulating design on FPGA 
board
 Expertise in AMBA high-speed bus protocols (AXI/AHB/APB)
 Experienced in RISC-V CPU verification
 Experienced in exploration, preparation, execution of verification plan and coverage analysis
 Back-annotated gate-level simulations and timing analysis
 Exposer in Formal verification for connectivity checks.
 Exposer in DFT functional verification for MBIST, PLL-BIST
 Mentored NCGs and made them productive in a short time