Extensive experience in SV-UVM environment including component developments (driver, 
monitors, checkers, coverage class). 
Experienced in writing SV Assertions for formal and dynamic simulations. 
Experienced in Leading SOC/IP verification. 
Experienced in GLS simulation bring-up and debugging. 
Experienced in leading (Verification) mixed signal chip. 
Formal verification hands on experience. 
Experience in working with chip with SPI, I2C, AMBA, Wishbone protocol. 
Experience in working with audio interface.