Senior Analog Layout Engineer
Block and top-level layout of analog circuits according to the design rules of the requested
technology (CMOS and BCD): 600nm, 350nm, 130nm, 40nm, 28nm, 22nm deep sub-micron CMOS.
Perform specific layout verifications: DRC, LVC, ERC, XOR, Antenna, 
ESD checksCalibre and Assura, parasitic C/RC extraction, Matching Check.
Full custom layout or update the old layout of mixed analog ? digital circuits: oscillator,
amplifier, comparator, regulator, DAC, ADC etc.