Deep knowledge in functional verification using advance verification methodologies such as VERA, VMM, OVM, 
UVM, SystemVerilog.
Worked on all stages of functional verification from defining verification strategy, test plan development, 
defining functional coverage goals, development of full verification testbench & environment components like 
driver, monitor, reference model, scoreboard, sequences, test cases to bug reporting, regression runs and 
coverage closure. 
Developed Test strategy derived from RISC V specifications for extensions I, M, A, C, Zfhmin, Za64rs, single and 
double precision floating points F And D and more. Also developed confirmatory test suit in assembly for each of 
the above extensions. 
Used SPIKE RISC-V reference model for tests suite development.
Block level, cluster or subsystem level and SOC level verification.
Developing testbench from basics. 
Developed sequence layering, virtual sequences.
Gate Level Simulations