-Expert knowledge in Object-Oriented and Aspect-Oriented programming using SystemVerilog, SystemC, e- Language/Specman, Vera
 	
 -Good understanding of RTL design using Verilog
 	
 -Development of TestBenches and Verification IPs compliant to RVM, VMM and UVM Methodologies
 	
 -Flexible in using client methodology as well as provide improvements if needed
 	
 -Proficient with the relevant technologies and tools: Mentor’s Modelsim/Questa , Synopsys VCS and DVE, Cadence’s NC-sim and irun
 	
 -Extensive experience in all phases of the Functional Verification process: Verification Strategy; specification of Test Plans, Coverage Plans, Metrics for TO release; designing and implementing complex verification environments featuring stimuli generators, monitors, scoreboards, cycle accurate or TLM models, performance checkers; compliance testing, stress testing, coverage completion
 	
 -Understanding of Network Processors and Controllers chip level architectures