ASIC Verification Engineer 

Technical Skills:
-SystemVerilog/UVM
-SVA
-C/C++
-SystemC
-Constrained random verification
-Python

- Upgrade existent UVM/VMM verification environments to accommodate new chip generations updates.
- Extend existing coverage models, add new coverage models, and close both functional and code coverage of 
various designs.
- Create testbench verification plan documents and track coverage goals through a high level hierarchical
verification plan (hvp) using Verdi for various designs.
- Using formal tools for reachability analysis.
- Build constrained random verification environments on subsystem level.
- Implement cycle accurate and transaction accurate reference models using SystemVerilog and SystemC.
- Use UVM Connect in SystemC reference models integration into UVM environments.