DFT Engineer with experience in DFT Insertion, Pattern generation, Verification, Delivery and Failure diagnostics.
Worked on a wide range of DFT methodology defined by leading EDA vendors like Synopsys and Mentor.

Simulation Tools: Synopsys VCS, Cadence ncsim, Mentor Graphics Modelsim. Formal verification : Cadence LEC.
Scan & ATPG: Mentor  Graphics  Tessent  shell,  Fastscan,  Testcompress,  Synopsys DFT compiler, BSD compiler, Tetramax.
Others: Synopsys Design Compiler, Synopsys Star Memory System, Mentor MBIST.
Languages Known: Verilog, vhdl, Perl, tcl