IP and SoC Verification Engineer
 	
 -Verification: System Verilog
 	
 -HDL languages: VHDL, VERILOG
 	
 -Writing synthesizable RTL code, time analysis and synthesis for FPGA
 	
 -Versioning control tools: SVN, GIT, Design Sync
 	
 -HDL simulators: Cadence – SimVisoin
 	
 -Programming Languages: C/C++
 	
 -EDA tools: Vivado/SDK
 	
 -IAR Embedded Workbench
 	
 -Cadence Vmanager, IMC
 	
 -Knowledge of ARM architecture and hardware/software experience with CortexM0,
 	
 -Operating system: Windows, Linux
 	
 -Application software: OpenOffice, MS Office, Microsoft Visual Studio