-A dynamic professional with years of experience in ASIC/IP Design Verification
 	
 -Adept in end-to-end development of ASIC/IP Verification Environment from requirement analysis to Test Plan creation, verification components coding (UVC/OVC monitors, drivers, sequences, scoreboards) test implementation (directed & constraint randomized) and coverage analysis
 	
 -Expertise in System Verilog based verification using UVM/OVM
 	
 -Hands on experience in UPF based verification of low power designs
 	
 -Domain expertise in PCIe6/CXL3, AMBA AXI, Image/Video Pre-Processing pipeline, MIPI-slimbus, DFx IPs and DDR Memories
 	
 -Hands on experience in SVA and formal verification
 	
 -Adept in developing re-usable Verification IPs
 	
 -Hands on experience in prototyping ASIC designs on FPGA and sound knowledge on Altera and Xilinx design flows
 	
 -Good communication, leadership and interpersonal skills