Senior Design Verification Engineer
 	
 -Expertise across various SoCs, specializing in IP/Block and SoC/Top level verification
 	
 -Proficiency extends to creating and managing test benches utilizing both C-driven and SV-UVM methodologies
 	
 -Verification methodologies: Metric driven verification, constrained random verification, UVM/SV, C driven verification around ARM/MIPS/tRoot CPUs, , eRM/e-specman, Formal (SVA, PS)
 	
 -Verification strategy, Verification plan and requirement management
 	
 -Programming: System Verilog, e, C, SystemC, perl, Tcl, Verilog, VHDL, Shell, Makefile, Python Ruby. Protocols: AMBA (APB, AHB and AXI), STBUS, SPI, I2S, I3C, I2C, DMA
 	
 -Verification environments qualification with fault injection approach
 	
 -Regression debug and triage
 	
 -Notion in DMS, RNM, SPICE
 	
 -Project management
 	
 -Tools (design and simulation): VERDI(VCS), Specman, Xcelium, NCism , Design_vision, , Spyglass, Max +,ModelSim, Quartz,Matlab & Simulink, Orcad (Pspice) Microwind, Pico_Express