Analog & Mixed Signal Verification Engineer
 	
-Professional skills: Mixed-signal verification, Analog/digital modeling, embedded system design
 	
-Programming languages: C/C++, Java, Matlab
 	
-Scripting languages: Python, Perl, Tcl, Bash, Skill
 	
-Languages: VHDL, Verilog, SystemVerilog, Verilog-a, VerilogAMS
 	
-Methodologies: UVM
 	
-Tools: Cadence verification toolchain
 	
-Version control tools: SOS, SVN, GitHub, Design Sync
 	
-Understanding and simulation of complex RF IPs
 	
-Hierarchical model development and simple MVSS(WREAL, RNM UDT)
 	
-Development of config files(Hierarchy editor)
 	
-AMS IP and simplified top level simulations running