-Expert knowledge in Object-Oriented and Aspect-Oriented programming using System Verilog, SystemC, e-Language/Specman
 	
 -Hands-on experience with formal verification methodology and tools
 	
 -RTL design using Verilog
 	
 -Development of TestBenches and Verification IPs compliant to RVM, VMM and UVM methodologies
 	
 -Flexible in using client methodology as well as providing improvements if needed
 	
 -Proficient with the relevant technologies and tools: Mentor's Modelsim/Questa, Synopsys VCS and DVE/Verdi, Cadence's NC-sim, irun/xrun and Jasper Gold
 	
 -Skilled in various verification methods; constrained random testing, coverage-driven verification, metric-driven verification
 	
 -Experience in block level and top-lev verification and different abstraction levels, as black-box, gray-box or white-box
 	
 -Hands-on experience on a wide range of protocols and the related industry standards: Ethernet, IPv4/v6, TCP/UDP, GDDR6, eMMC, PCIe/NVMe, NFC, IEEE1588, MPLS, JEDEC, IEEE 802.3