AMS design and verification Engineer
 	
-VHDL/ SystemVerilog/ VerilogAMS/ UVM/C
 	
-Development of AMS design verification environment
 	
-Professional skills:
 	
 -Mixed-Signal Functional Verification, Analog circuits modeling(Verilogams, wreal), Analog IP verification
 	
-Programming languages:
 	
 -VHDL, SystemVerilog, VerilogAMS, C
 	
-Tools:
 	
 -Cadence Virtuoso, Cadence SimVision, Altera Quartus II, Altera ModelSim, Eclipse, Matlab, Vmanager, Virtuoso Analog Design Environment, Labview, CAD Microwave Office(MWO)
 	
-Protocols knowledge:
 	
 -System buses (Avalon), Serial protocols (UART, SPI, I2C), DMAs