Verification engineer skilled in module-level, subsystem and SoC verification
 	
Areas of expertise include:
 	
 -SystemVerilog and UVM
 	
 -Coverage driven verification
 	
 -Coverage analysis and closure
 	
 -Regression debug
 	
 -Verification Methodologies: UVM
 	
 -Verification Languages: SystemVerilog, C
 	
 -Design Languages: Verilog, VHDL
 	
 -Revision and Control Systems: Perforce, Git, DesignSync, SubVersion
 	
 -Tools: SimVision, Verdi, vManager, IMC, Certitude, QuestaSim
 	
 -Protocols: AHB, APB, AXI, SPI, I2C, UART
 	
 -Operating Systems: Windows, Linux