Full RTL to GDSII flow for high performance and low-power ICs (down-to 10nm), specialized in timing-closure. Flows:  IC design flow from RTL to GDSII, either at macro or top levels. partitioning, budgeting, synthesis, STA, DFT, floorplan, CTS, place&route, timing-closure, DRC checks, formal verification 
Main tools:Synopsys ICC2/ DCT/ PrimeTime/ Formality 
Mentor Calibre 
Computing: knowledges in various languages as Tcl, Shell, VBA, Java