-Digital IC Design Engineer with over 12 years in chip/block level architecture definition and RTL design
 	
-Leading complex projects and implementation/integration (high speed) interface protocols and subsystems within SoC at top-tier companies such as Kandou, Intel, and Cadence
 	
-Adept at driving innovation and delivering high-quality solutions
 	
-Key Skills:
 	
 -RTL design - Verilog/SystemVerilog
 	
 -Architecting, Micro-architecting
 	
 -Technical lead of designs and integration of complex IP subsystems
 	
 -Technical presentations & customer support
 	
 -(High-speed) digital IPs - CXL/PCIe, PIPE, AMBA/AXI protocols
 	
 -Solid grasp of simulation concepts such as regression testing, UVM, functional coverage, assertions
 	
 -Deep understanding of release process - SDC constraints, STA timing analysis, Lint - Superlint/Spyglass, CDC, checklists
 	
 -Special IP product development - mitigation techniques/safety mechanisms, ISO26262, FMEDA report, diagnostic coverage