Digital Design and Verification Engineer
Verilog/VHDL: Experienced
Embedded C: very good
Digital Simulators: VCS (Expert), ModelSim (Basic), Fast spice simulators [XA/Nanosim] (Expert)
Programming: Java, Android development, C++, MATLAB (coding / Simulink simulation)

Strongly adhering to the following verification concepts:
Coverage Driven Verification
Constrained Random Verification

Testing any new features/functionality/designs including:
defining the stimulus, checks and coverage that needs 
to be implemented
Implementing the new stimulus, adding the required
Building, Analyzing coverage models + fixing any hole