Digital Design Team 03
Experience level: 90 years
Experience
This team consists of 8 Engineers - 1 team lead and 7 experienced ASIC Physical Design Engineers They have a combined total of 90+ Years of experience in. The team have worked on multiple complex SoC Level Projects, Baseband ASIC's targeted towards the latest technologies
Expertise
Number of Engineers: 8 Total Years of Experience: 90+ Years Core Expertise: PHYSICAL Design, STA, PrimeTime, Digital Layout, DFT
Tools
ASIC implementation and physical verification for RTL through to GDS 2 Synthesis STA Timing Closure (Primetime) DFT and formal verification(Test Compiler and Tetra MAX) Formality Equivalence checking TCL and Perl scripting
Contact Us
+353 91 444 168
info@chipright.com
Unit 8B, Galway Technology Centre, Galway, Ireland